`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:38:47 11/22/2010 
// Design Name: 
// Module Name:    vga_stripes_top 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module vga_stripes_top(mclk, btn, hsync, vsync, red, green, blue);

input wire mclk;
input wire [3:0] btn;
output wire hsync, vsync;
output wire [2:0] red, green;
output wire [1:0] blue;

wire clk25, clr, vidon;
wire [9:0] hc, vc;

assign clr = btn[3];

clk_div U1(.mclk(mclk), .clk25(clk25));

vga_640_480 U2(.clk(clk25), .clr(clr), .hsync(hsync), .vsync(vsync), .hc(hc), .vc(vc), .vidon(vidon));

vga_matrix U3(.vidon(vidon), .hc(hc), .vc(vc), .red(red), .green(green), .blue(blue));

endmodule
